1. Field of the Invention
The present invention relates to the field of synchronization and timing of operation in a computer system, in particular to clocking schemes for use on a high speed local bus.
2. Description of the Related Art
As computer systems such as microcomputer systems and the class of computer systems commonly known as workstations, are developed to run at ever faster speeds, it is desirable to be able to sample (or read) data on a bus on every clock cycle. For example, it is desirable that a data sending device send data over a bus, during one clock cycle, to a data receiving device which receives that data during the same clock cycle; this means that a data transaction between the sending and the receiving devices will occur every clock cycle, resulting in maximum throughput of data over a given time. A clock cycle for a computer system is commonly measured in MegaHertz (MHz). The measurement refers to the number of times an oscillator completes a phase change cycle in one second, a MegaHertz representing one million such changes per second. A clock cycle is used for timing and synchronization purposes within a computer system, and the same clock signal is often used as the synchronization reference for both the data sending device and the data receiving device. In order to sample data on a bus, the data must be presented onto the bus by a transmitting unit and the data must be stabilized on the bus, i.e. be in a state that reflects the actual data presented by the transmitting unit. Only after the data is stable may the data be accurately sampled by a receiving unit.
Typically, a receiving unit will sample data on the rising edge of a clock cycle. Likewise, a transmitting unit will begin transmission of data on a rising edge. In known systems, transmitting units within a computer system would "hold" the data on the bus for a period of time after the transmitting unit has received the rising edge of a clock cycle, so that a receiving unit may accurately sample data on the bus. This "hold" time is especially critical when designing a high speed system. As chip components begin to operate faster, this hold time becomes shorter and shorter.
Referring to FIG. 1, assuming that a transmitting and receiving unit are synchronized from the same clock source, that the receiving unit is sampling the data on the bus on the rising edge of the clock cycle and that data is transmitted every clock cycle, CLK signal 101 and DATA signal 102 are illustrated. The areas 103 reflect where the data on a bus is unstable and the areas 104 reflect where the data on bus are stable. When data is transmitted onto the bus, a certain amount of start-up time is incurred which is reflected in the areas 103.
Assuming a start-up time where the data is unreliable, the data must be sampled within a portion of the clock cycle time where the data is reliable (i.e. stable). As the data is being sampled on the bus at a rising edge of a clock cycle (e.g. edge 105), the data must be stable for the period of time before new data is placed on the bus (i.e. there is a new clock cycle), for example at point 106. A hold time 107, is the time lapse between the rising edge sample time 105 and the transmission of data time 106. Thus, timing becomes critical so that data can be accurately sampled.
Currently, it is not commercially viable for vendors of chip components to guarantee an acceptable minimum data hold time under all operating conditions (i.e. under varying operating temperatures and under varying load conditions). As a result, most suppliers of data driving components often specify a zero (0) nanosecond minimum hold time for their components. However, receiving components have been designed to tolerate a zero nanosecond hold time, i.e. the data need not be held stable on the bus after the receiving unit has been clocked. Thus, it is critical that a receiving unit's clock source be at a rising edge prior to a clock source of a transmitting unit being at a rising edge to signal change of data. This has led to timing and synchronization problems, particularly when operating speeds approach 33 MHz.
As an additional consideration, within any given circuit, a certain amount of propagation delay will be incurred between components that are receiving a signal in a sequential or serial fashion. With a signal which provides a clock cycle, this propagation delay results in a small amount of skew that occurs between the clock inputs of the different components. As discussed above, this skew may cause problems when attempting to transmit data every clock cycle, especially with a zero nanosecond hold time. This is illustrated in FIG. 2. In FIG. 2, a data receiving unit's clock 205 lags a data transmitting units clock 206. This occurs because a clock source is routed physically to the transmitting unit before it gets to the receiving unit. Data 207 on the bus is comprised of valid or reliable areas 204 and invalid or unreliable areas 203. As data will be sampled on a rising edge of a data receiving unit's clock 205, e.g. sample points 201 and 202, with a zero nanosecond hold time, the data sample will be unreliable.
Several known approaches have been utilized to address this problem. A first approach is for the designer to hold the data transmitted onto the bus for multiple clock cycles (e.g. two), thus creating "hold time" based upon a complete clock cycle. This has the undesired effect of slowing computer system operation. A second approach is to route the clock signal so that a receiving unit has a clock input that precedes a transmitting unit's clock input and to utilize receiving components that tolerate zero (0) nanosecond input data hold times. In such a configuration, valid data would be sampled as illustrated in FIG. 3. In FIG. 3, a data receiving unit's clock 305, leads a data transmitting unit's clock 306. Data 307 on a bus is comprised of reliable areas 304 and unreliable areas 303. Here, sample points 301 and 302 will sample in areas 304 where the data is reliable. However, this approach is not viable where a unit may both send and receive data. When a unit may both send and receive data, the clock signal to the unit may be skewed in the proper direction for one transaction, e.g. transmit data, but would be skewed in the improper direction for the other transaction, e.g. receive data, bringing out the problem discussed with reference to FIG. 2.
A third approach known in the art, is to utilize components with dual clock inputs. In this approach, the components have a first clock input, e.g. LDCLK, which is used when the unit is receiving data and a second clock input, e.g. CLK for all other functions. Such a circuit utilizing this approach is illustrated in FIG. 4. In FIG. 4 when Unit A 401 wishes to transmit data to Unit B 402, certain handshaking signals are exchanged between the two units (not illustrated). Unit A 401 and Unit B 402 both have CLK input pins 405 and 406, and LDCLK input pins 407 and 408, respectively. Each of the units is further bidirectionally coupled to a data bus 411, via data lines 409 and 410, respectively. In operation, a LDCLK signal 404 will always lead a CLK signal 403. This is accomplished by utilizing means which will phase shift the two clock signal sources. Referring now to FIG. 5, the LDCLK signal 404 will lead the CLK signal 403 for a predetermined period of time. So, the LDCLK signal 404 will trigger a sample point 502 for the receiving unit to sample, which is within a period of time where the data is valid, e.g. area 504.
This solution has the deficiencies of requiring two different clocks and additional circuitry to insure that the two clocks are phase shifted in a fixed manner. A clock source that provides fixed phase shifted output may also be utilized, but that adds to the cost of the system.
It is an object of the invention to provide a method and apparatus for improved clocking in a computer system for use with a high speed data bus where a single clock source is used with components that send data and where a data transaction occurs during each clock cycle.
It is also known that the utilization of dual clock circuits may result in synchronization problems within each unit. Such a synchronization problem arises within the internal circuitry of a unit causing skews which may result in invalid or unreliable data being transmitted or received. It is a further object of the invention to provide a circuit design technique where such synchronization problems within a unit may be addressed.